One-wire device with A-to-D converter

ABSTRACT

A low power integrated circuit having analog to digital conversion circuitry capable of receiving a plurality of analog signals and converting them to a digital value. The digital value is then transmitted, upon request, over a single wire bus. The accuracy of the analog to digital conversion circuitry can be calibrated via trim codes stored in an onboard EPROM.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a device capable of changing ananalog signal to a digital signal and then communicating the convertedsignal over a single wire bus to a host. More particularly, the presentinvention relates to a quad input analog to digital converter whichconverts a plurality of analog signals into a plurality of digitalsignals that can be communicated over a single wire bidirectionalcommunication bus.

[0003] 2. Description of Related Art

[0004] Analog to digital converters (A-to-D) converters have becomecommon in the electronic industry. In general, an A-to-D converterreceives an analog signal and converts the signal into a digital signal.The resulting digital signal is sent in parallel form or in serial formover multi-wire busses.

[0005] When an analog signal is sent over a long wire connected to ahost system, the integrity of the analog signal decreases over thelength of the connection. Conversely, a digital signal's integrity ismuch less likely to decrease over the same long wire connection. Yet, adrawback of A-to-D converters is that they consume a large amount ofenergy while performing an A-to-D conversion. Furthermore, A-to-Dconverters are difficult to incorporate into an analog sensor that isremotely positioned to take an analog reading in a remote location.A-to-D converters require multiple wires to connect the A-to-D converterto a system which uses the digitized output of the converter.

SUMMARY OF THE INVENTION

[0006] There is a need for a low power, A-to-D converter that can becoupled directly to an analog sensor and provide a digitized signal overas few wires as possible and over a long length of wire to a system orhost system that is to use the digitized signal. Such a device wouldincrease the integrity of the signal sensed at a remote location becausethe signal would be digitized at the remote location instead of aftertraveling the full, long length of the wire connecting the remotelyplaced analog device to a host system.

[0007] The present invention responds to this need by providing anA-to-D converter that takes an analog voltage level on one of its inputpins and converts the analog voltage level to a digital words which canbe output via a single wire bus. The single wire bus can be a one-wiredata bus which uses a one-wire protocol.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various objects and advantages of this invention will becomeapparent and more readily appreciated from the following description ofthe exemplary embodiments of the present invention taken in conjunctionwith the accompanying drawings, of which:

[0009]FIG. 1 depicts a block diagram of an exemplary one-wire A-to-Dconversion device.

[0010]FIG. 2 depicts an exemplary one-wire A-to-D converter incommunication with a host and the hierarchical structure for a preferredone-wire protocol.

[0011]FIG. 3 depicts an exemplary hardware configuration for a one-wireconnection between a host device and a one-wire input of an exemplaryone-wire A-to-D conversion device.

[0012]FIG. 4 depicts a block schematic of an exemplary A-to-D convertersystem found in an exemplary device.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS OF THE PRESENTINVENTION

[0013] An exemplary embodiment of the present invention is an A-to-Dconverter with a one-wire interface. The A-to-D converter is preferablya quad A-to-D converter. In generic terms, the preferred A-to-Dconverter with a one-wire interface comprises an A-to-D converter withfour inputs so that it can convert four different analog signals todigital signals. The signals are converted from an analog voltage levelto a digital word which can be output on a one-wire bus. The preferredone-wire bus protocol is that which was created by Dallas Semiconductorof Dallas, Tex. Of course it is understood that other one-wire busprotocols may be used to communicate the digital word from the exemplaryembodiment to another device.

[0014] Many types of analog sensing are preformed with a wide variety ofdevices. Temperature, flow, pressure, humidity, direction, flex, speed,volume, fluid level, position, resistance, and distance are a fewexamples of physical properties that may be expressed as analogvoltages.

[0015] Manufacturers of the analog devices would like to convert theanalog signals to a digital signal at the point of measurement. Due tothe sensors being placed in remote locations, there is a need for aneconomy of physical connections or wires to the remote sensor.Furthermore, there is a need to have the analog signal converted to adigital signal at the remote location and then to send the digitalsignal over a long length of wire to a host, instead of sending theanalog signal through the wire. The digital signal will not degrade asmuch as an analog signal over the same length of wire.

[0016] Referring now to FIG. 1 an exemplary embodiment of the presentinvention is shown in the form of the major junction blocks of theA-to-D converter with a one-wire bus 10. The preferred A-to-D converterwith a one-wire bus 10 contains a factory-lasered registration numberthat includes a unique 48-bit serial number an 8-bit CRC, and an 8-bitfamily code. These are all contained in the 64-bit lasered ROM 12. The64-bit ROM 12 portion of the exemplary A-to-D device 10 not only createsan absolutely unique electronic identification for the device, but alsocan be used to locate and address the A-to-D device 10 in order toexercise its control functions.

[0017] Referring now to the block labeled parasitic power 14, theexemplary A-to-D device 10 obtains its power either from the one-wirebus 16 or through its V_(DD) pin 18. Without the V_(DD) supply thedevice stores energy on an internal parasitic capacitor 20 duringperiods when the signal line (one-wire bus) is high and continues tooperate off the parasitic capacitor 20 power source during low signalson the one-wire data bus while the capacitor waits until the one-wiredata line 16 returns to a high state to replenish the energy in theparasitic capacitor 20. Diodes 22 are connected in this parasitic powercircuit 14 to aid the parasitic power process. If multiple one-wireA-to-D devices 10 are operating simultaneously on the same one-wire bus16, then a strong pull-up of the one-wire bus 16 to 5 volts or a V_(DD)power supply is required.

[0018] The one-wire function control circuitry 24 interprets one wirefunction commands. Although, any single wire communication protocolcould be used, the preferred exemplary one-wire A-to-D converter deviceuses the standard Dallas Semiconductor one-wire protocol for datatransfers. The one-wire function control 24 handles communication withthe one-wire bus 16. FIG. 2 depicts a hierarchical structure forone-wire protocol. Communication to and from the A-to-D device 10preferably requires a single bi-directional line 16 that is typicallyconnected to a port pin of a microcontroller or bus master 30. Theone-wire bus master 40 must first provide one of seven ROM functioncommands, 1)read ROM, 2) match ROM, 3) search ROM, 4) conditional searchROM, 5) skip ROM, 6) overdrive-skip ROM, or 7) overdrive-match ROM. Uponcompletion of an overdrive ROM command byte executed at standard, theA-to-D device's one-wire bus 16 will enter an overdrive mode where allsubsequent communication occurs at a higher speed.

[0019] The present preferred exemplary embodiment is compatible withboth multi-drop and overdrive aspects of the one-wire protocol. Themulti-drop ability allows many one-wire devices to be connected to thesame one-wire bus 16.

[0020] The register access and conversion control block of FIG. 1decodes commands that the exemplary A-to-D converter device 10understands and modifies the appropriate registers within the device.The registers are found in the channel control and register portion 28of the circuitry. The internal registers control many aspects of theA-to-D conversion processes. Commands, such as write registers, readregisters and convert, are decoded in register access and conversioncontrol block 26 and sent to the channel control and registers block 28where the registers are updated.

[0021] Referring now to the channel control and register block 28, theregisters will now be discussed. Table 1 and Table 2 (both below)indicate preferred registers for use in the present A-to-D device 10.All of the registers of the exemplary one-wire A-to-D device 10 aremapped into a linear memory range of 24 adjacent bytes organized asthree 8-byte pages. The first page, called conversion read-out containsthe memory area where the results of a conversion for the bus master 40to read is placed. Starting with the channel at the lowest address, eachchannel has an area of 16-bits assigned for the conversion result (seeTable 1). The power-on default for the conversion read-out registers isall zeros. Regardless of the resolution requested, the most significantbit of the conversion is always at the same bit location. If less than16 bit resolution is requested, the least significant bits of theconversion result will be filled with zeros in order to generate a16-bit result. For applications that require less than four analoginputs, the D input should be used first. The advantage here is thatwhen reading the conversion results one reaches the end of the page and,with it, the CRC sooner and thereby minimizes the traffic on theone-wire bus 16. TABLE 1 Ad- dress bit 7 bit 6 bit 5 bit 4 bit 3 bit 2bit 1 bit 0 00 A A A A A A A LSBIT A 01 MSBIT A A A A A A A A 02 B B B BB B B LSBIT B 03 MSBIT B B B B B B B B 04 C C C C C C C LSBIT C 05 MSBITC C C C C C C C 06 D D D D D D D LSBIT D 07 MSBIT D D B B D D D B

[0022] Table 2 depicts the control and status information for allchannels. The control and status information is located in memory page1. Each channel is assigned 16 bits. The four least significant bits,called RC3 to RC0, are an unsigned binary number that represent thenumber of bits to be converted. A code of 1111 (15 decimal) willgenerate a 15-bit result. For a full 16-bit conversion the code numbershould be 0000. The next two bits beyond RC3 will always read 0; atpresent they have no function. TABLE 2 Address bit 7 bit 6 bit 5 bit 4bit 3 bit 2 bit 1 bit 0 08 0E-A 0C-A 0 0 RC3-A RC2-A RCl-A RC0-A 09 POR0 AFH-A AFL-A AEH-A AEL-A 0 IR-A 0A 0E-B 0C-B 0 0 RC3-B RC2-B RCl-B RC-B0B POR 0 AFH-B AFL-B AEH-B AEL-B 0 IR-B 0C 0E-C 0C-C 0 0 RC3-C RC2-CRCl-C RC0-C 0D POR 0 AFH-C AFL-C AEH-C AEL-C 0 IR-C 0E 0E-D 0C-D 0 0RC3-C RC2-D RCl-D RC0-D 0F POR 0 AFH-D AFL-D AEH-D AEL-D 0 IR-D

[0023] The next bits, OC (output control) and OE (enable output) controlthe alternate use of a channel as output (AIN-A, AIN-B, AIN-C, AIN-D)32. for normal operation as analog input the OE bit of a channel needsto be 0, rendering the OC bit to a don't care. With 0E set to 1, a 0 for0C will make the channel's output transistor conducting, a 1 for 0C willswitch the transistor 30 off. With a pull-up resistor to a positivevoltage, for example, the OC bit will directly translate into thevoltage equivalent of its logic state. Enabling the output 32 does notdisable the analog input 32. Conversions remain possible, but willresult in values close to 0 if the transistor 30 is conducting.

[0024] The IR bit in the second byte of a channel's control and statusmemory selects the input voltage range. Preferably, with IR set to 0,the highest possible conversion result is reached at 2.55 V. Setting IRto 1 requires an input voltage of 5.10 V for the same result. The nextbit beyond IR does not presently have a function.

[0025] The next two bits, AEL alarm enable low and AEH alarm enablehigh, control whether the device 10 will respond to the ConditionalSearch command if a conversion results in a value higher (AEH) than orlower (AEL) than the channel's alarm threshold voltage as specified inthe alarm settings. The alarm flags AFL (low) and AFH (high) tell thebus master 40 whether the channel's input voltage was beyond the low orhigh threshold at the latest conversion. These flags are clearedautomatically if a new conversion reveals a non-alarming value. They canalternatively be written to 0 by the bus master 40 without a conversion.

[0026] The next bit of a channel's control and status memory presentlyreads 0 and cannot be changed to 1 in the exemplary embodiment. The PORbit (power on reset) is automatically set to 1 as the device performs apower-on reset cycle. As long as this bit is set the device will alwaysrespond to the Conditional Search command in order to notify the busmaster 40 that the control and threshold data is no longer valid.

[0027] The registers for the alarm threshold voltages of each channelare located in memory page 2 with the low threshold being at the loweraddress (See Table 3). The power-on default thresholds are 00h for lowalarm and FFh for high alarm. The alarm settings are always eight bits.For a resolution higher or equal to eight bits the alarm flag will beset if the eight most significant bits of the conversion result yield anumber higher than stored in the high alarm register (AFH) or lower thanstored in the low alarm register (AFL). For a resolution lower thaneight bits the least significant bits of the alarm registers areignored. TABLE 3 Ad- dress bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit0 10 MSBL-A A A A A A A LSBL-A 11 MSBH-A A A A A A A LSBH-A 12 MSBL-B BB B B B B LSBL-B 13 MSBH-B B B B B B B LSBH-B 14 MSBL-C C C C C C CLSBL-C 15 MSBH-C C C C C C C LSBH-C 16 MSBL-D D D D D D D LSBL-D 17MSBH-D D D D D D D LSBH-D

[0028] In more general terms the registers allow each one of four analoginput pins 32 A, B, C, D to be configured differently. For example, foreach input pin 32 the A-to-D conversion can operate with differentresolutions. The resolution of the A-to-D converter is configurable bythe user. The resolution can be specified by what is stored in theregisters. The resolution can be, in the preferred embodiment, from 1 to16 bits. This provides the user with a very versatile device.

[0029] Furthermore, the registers can be set or the device can beprogrammed to get alarms for each channel. The alarms can be for lowhigh or both low and high alarms. Each channel can have different alarmsettings. The alarms can be communicated, via the one-wire bus 16, tothe host system 40 when and if they are tripped.

[0030] The CRC generator circuitry 34 is used as a data integrity check.The preferred embodiment incorporates a 16-bit CRC generator which aidsin the determination of data integrity or bit error problems duringtransmission and receipt of information over the one-wire bus 16.

[0031] Still referring to FIG. 1, the 4-to-1 analog multiplexer 36 isconnected to the analog inputs A, B, C and D (AIN-A, AIN-B, AIN-C,AIN-D, respectively) 32, A, B, C, D. The present exemplary embodimentcan only convert one analog channel at a time. Thus, when the convertcommand is presented to the device 10, the channel which is to beconverted is also communicated. The 4-to-1 analog multiplexer 36connects which ever one of the four channels is to be converted to theA-to-D converter circuitry 38.

[0032] The A-to-D converter circuitry 38, of course, is used to convertthe analog signal to a digital signal and then provide the digitalsignal to the registers so that the converted signal can be formattedinto one-wire data protocol and sent to the host 16. FIG. 4 depicts amore detailed block diagram of the 4 to 1 multiplexer and A-to-Dconverter. The circuit labeled A/D INPUT MUX 50 corresponds to the4-to-1 Analog Multiplexer shown in FIG. 1. The A/D INPUT MUX 50 is usedto select one of the four input channels to feed through to the analoginput (AIN) of the rest of the A-to-D circuitry.

[0033] The circuitry labeled A/D Bandgap 52 is a portion of thereference voltage generator portion of the A/D converter circuitry. Anoutput from the A/D Bandgap 52 is labeled VREFIN 54. VREFIN 54 isgenerally a voltage of 1.262 volts due to inherent properties of siliconcircuitry. Thus, VREFIN 54 is passed to the A/D VREF scaler circuit 56which applies a voltage gain to thereby generate the needed 1.280 voltsas VREF 58. 1.280 volts is half of the preferred full scale voltageinput of 2.560 volts.

[0034] The block labeled EPROM Trim 60 which provides trim value ofresistance or capacitance to calibrate the band gap 52 and voltagereference circuitry 56. The EPROM Trim circuitry 60 can also be used tocalibrate the RC or ring oscillator clock (not shown) which is withinthe present exemplary one-wire A-to-D device 10.

[0035] At present the EPROM 60 is programmed and the device 10 iscalibrated during the manufacturing process. It is understood that theEPROM 60 could be programmed with trim codes and the device could becalibrated by the end user of the device 10. Thus, if aging of the partmakes component parameters shift, then the EPROM Trim circuitry 60 canbe programmed or reprogrammed to compensate for the shift.

[0036] In the exemplary device there are 32 EPROM bits and the bitseffect a number of circuits within the present exemplary device 10. Someof the bits change the resistance of variable resistors in the band gapcircuit 52. Other bits are used to change the gain in the A/D VREFscaler circuit to compensate the circuitry in order to provide anaccurate 1.28 volt output. Still other bits may be used by the A/Dresidual doubler circuit 62.

[0037] The A/D residual doubler 62 is used to help determine themagnitude of the received analog voltage. The AIN signal 64 (theselected analog input signal) is provided to a comparator circuit,within the A/D residual doubler 62, and compared to 1.280 volts. Theoutput of the comparator is the most significant bit of the comparisonresult. If the bit was a zero, meaning that the selected analog inputvoltage was less than 1.280 volts, the residual is determined bydoubling the input voltage. If the bit was one, meaning that the analoginput was greater than the 1.280 volt (half full scale voltage), thenthe residual is determined by doubling and then the input voltage andsubtracting the full scale range (2.560 volts). The residual is fed backinto the comparator and compared with the 1.280 volts to determine thenext bit and the new residual value. This process continues until theselected resolution is achieved.

[0038] An important aspect of the present embodiment is that the usercan select the amount of resolution needed. Further, unlike other A-to-Dconverters which depend heavily on precise matching of MOS devices inthe comparator and voltage reference, the present device can compensatefor mismatches and inaccuracies by trimming them out using the EPROMtrim codes. (See above discussion of the EPROM 60).

[0039] Still referring to FIG. 4, the A/D bias circuit 66 provides biascurrent to the analog components, such as comparators, operationalamplifiers or any circuit that requires a mirrored current source. TheA/D bias circuit 66 generates reference currents for each analog devicein the device that requires a bias current.

[0040] Referring back to FIG. 1 and reviewing what was discussed above,each analog input (AIN-A, AIN-B, AIN-C, AIN-D) includes NMOS transistor30. Each NMOS transistor is a very high gain device. If the end user ofthe exemplary device does not need to use all the input pins, but doesneed an open drain output for another component in the user's circuitdesign, then NMOS device 30 can be used. In essence, the NMOS device 30allows an input channel that is not being used to have a dual functionas an open drain output pin. Such an open drain device can sink enoughcurrent to meet the requirements of, for example, a LED device.

[0041] Again to review, the present exemplary one-wire A-to-D converterprovides a user with a multitude of useful and advantageous options. Theone-wire interface provides an economy of wiring connections between ahost system and the exemplary one-wire A-to-D converter. Only one singlewire connection is required. The exemplary device also allows the userto program the digital resolution required for the specific task. Thepresent A-to-D converter can be programmed to have from 1 to 16 bits ofresolution on each of the four channels.

[0042] The present A-to-D circuitry requires approximately sixty toeighty microseconds per bit of resolution. The present device would notbe considered a high-speed A-to-D converter in today's technology, butwould be considered a very low power A-to-D converter. For example, thedevice may take 500 microseconds to perform an A-to-D conversion andsend the result over the single wire bus, but will only sink less thanone-half a miliamp during the conversion process. This is an order ofmagnitude less than any high speed A-to-D converter which performs acomparable task. The trade-off is between computing speed and therequired power to perform the A-to-D conversion task.

[0043] Still another advantage of the present one-wire A-to-D converteris that it can be trimmed using an EPROM either during manufacturing orby the end user. Thus, the A-to-D conversion circuitry can be accuratelytrimmed theoretically a moment before the device is to be used.

[0044] The following are preferred commands used by the presentexemplary one-wire A-to-D converter device 10.

[0045] READ MEMORY:

[0046] The Read Memory command is used to read conversion results,control/status data and alarm settings. The bus master follows thecommand byte with a two byte address that indicates a starting bytelocation within the memory map. With each subsequent read data time slotthe bus master receives data from the exemplary one-wire A-to-Dconverter starting at the supplied address and continuing until the endof an eight-byte page is reached. At that point the bus master willreceive a 16-bit CRC of the command byte, address bytes and data bytes.This CRC is computed by the exemplary one-wire A-to-D converter 10 andread back by the bus master 40 to check if the command word, startingaddress and data were received correctly. If the CRC read by the busmaster 40 is incorrect, a Reset Pulse must be issued and the entiresequence must be repeated.

[0047] WRITE MEMORY:

[0048] The Write Memory command is used to write to memory pages 1 and 2in order to set the channel-specific control data and alarm thresholds.The bus master 40 will follow the command byte with a two byte startingaddress and a data byte. A 16-bit CRC of the command byte, addressbytes, and data byte is computed by the exemplary one-wire A-to-Dconverter 10 and read back by the bus master 40 to confirm that thecorrect command word, starting address, and data byte were received. Theexemplary one-wire A-to-D converter then copies the data byte to thespecified memory location. The bus master then receives a copy of thesame byte but read from memory for verification. If the verificationfails, a Reset Pulse should be issued and the current byte addressshould be written again.

[0049] If the bus master does not issue a Reset Pulse and the end ofmemory was not yet reached, the exemplary one-wire A-to-D converter 10will increment its address counter to address the next memory location.The new two-byte address will also be loaded into the 16-bit CRCgenerator as a starting value. The bus master will send the next byteusing eight write time slots. As the exemplary one-wire A-to-D converter10 receives this byte it also shifts it into the CRC generator and theresult is a 16-bit CRC of the new data byte and the new address. Withthe next sixteen read time slots, the bus master 40 will read this16-bit CRC from the exemplary one-wire A-to-D converter to verify thatthe address incremented properly and the data byte was receivedcorrectly. If the CRC is incorrect, a Reset Pulse should be issued inorder to repeat the Write Memory command sequence.

[0050] The decision to continue after having received a bad CRC or ifthe verification fails is made entirely by the bus master 40. Writeaccess to the conversion read-out registers is not possible.

[0051] CONVERT:

[0052] The Convert command is used to initiate the analog to digitalconversion for one or more channels at the resolution specified inmemory page 1, control/status data. The conversion takes between 60 and80 μs every time the convert command is issued. For four channels with12 bit resolution each, as an example, the convert command will not takemore than 4×12×80 μs plus 160 μs offset, which totals to 4 ms. If theexemplary one-wire A-to-D converter 10 gets its power through the V_(DD)pin 18, the bus master 40 may communicate with other devices on theone-wire bus 16 while the exemplary one-wire A-to-D converter 10 is busywith A/D conversions. If the device is powered entirely from theone-wire bus 16, the bus master 40 should provide a strong pull-up to 5Vfor the estimated duration of the conversion in order to providesufficient energy. The present exemplary embodiment preferably uses lessthan 5 milliwatts of power while performing a conversion.

[0053] The conversion is controlled by the input select mask (Table 4)and a read-out control byte (Table 5). In the input select mask the busmaster 40 specified which channels participate in the conversion. Achannel is selected if the bit associated to the channel is set to 1. Ifmore than one channel is selected, the conversion takes place onechannel after another in the sequence Input A, B, C, D, (32 A, B, C, D)skipping those channels that are not selected. The bus master 40 canread the result of a channel's conversion before the conversion of allthe remaining selected channels is completed. In order to distinguishbetween the previous result and the new value the bus master 40 uses theread-out control byte. This byte allows to preset the conversionread-out registers for each selected channel to all 1's or all 0's. Ifthe expected result is close to 0 then one should present to all 1's orto all 0's if the conversion result will likely be a high number. Inapplications where the bus master 40 can wait with reading until allselected channels are converted, a preset of the read-out registers isnot necessary. TABLE 4 Input Select Mask (Conversion Command) bit 7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 don't care D C B A bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit 1 bit 0 set D clear D Set C Clear C Set B ClearB Set A Clear A

[0054] TABLE 5 Read-Out Control (Conversion Command) Set ClearExplanation 0 0 no preset, leave as is 0 1 present to all 0s 1 0 presetto all 1s 1 1 (illegal code)

[0055] Following the Convert command byte, the bus master 40 transmitsthe input select mask and a read-out control byte. Now the bus master 40reads the CRC16 of the command byte, select mask and control byte. Theconversion will start not earlier than 10 μs after the most significantbit of the CRC is received by the bus master 40.

[0056] With parasitic power supply 14, the bus master 40 must activatethe strong pull-up within this 10 μs window for a duration that isestimated as explained above. After that, the data line 16 returns to anidle high state and communication on the bus can resume. The bus master40 would normally send a reset pulse to exit the Convert command. Readdata time slots generated after the strong pull-up has ended, but beforeissuing a reset pulse should result in all 1's if the conversion timewas calculated correctly.

[0057] With V_(DD) power supply 18, the bus master 40 may either send areset pulse to exit the Convert command or continuously generate readdata time slots. As long as the one-wire A-to-D converter 10 is busywith conversions, the bus master 40 will read 0's. After the conversionis completed the bus master 40 will receive 1's instead. Since in anopen-drain environment a single 0 overwrites multiple 1's, the busmaster 40 can monitor multiple devices converting simultaneously andimmediately knows when the last one is ready. As in the parasiticallypowered scenario the bus master 40 finally has to exit the Convertcommand by issuing a rest pulse.

[0058] ONE-WIRE BUS SYSTEM:

[0059] The one-wire bus 16 is a system which has a single bus master 40and one or more slaves. The preferred one-wire A-to-D converter 10 is aslave device. The discussion of this bus system is broken down intothree topics: hardware configuration, transaction sequence, and one-wiresignaling (signal types and timing). A one-wire protocol defines bustransactions in terms of the bus state during specific time slots thatare initiated on the falling edge of sync pulses from the bus master 40.It is understood that other single wire systems or protocols maypotentially be used with the present A-to-D conversion device withoutstraying from the spirit of the invention.

[0060] The preferred one-wire bus 16 has a single line by definition; itis important that each device on the bus be able to drive the bus at theappropriate time. To facilitate this, each device attached to theone-wire bus 16 must have open drain or 3-state outputs. The one-wireport 70 of the one-wire A-to-D converter device 10 is open drain with aninternal circuit equivalent to that shown in FIG. 3. A multidrop busconsists of a one-wire bus 16 with multiple slaves attached. At regularspeed the one-wire bus has a maximum data rate of 16.3k bits per second.The speed can be boosted to 142 k bits per second by activating theOverdrive Mode. The one-wire bus requires a pull-up resistor 72 ofapproximately 5 kΩ to 1.5 kΩ.

[0061] The idle state for the one-wire bus 16 is high. If for any reasona transaction needs to be suspended, the bus MUST be left in the idlestate if the transaction is to resume. If this does not occur and thebus is left low for more than 16 μs (regular speed), one or more deviceson the bus may be reset.

[0062] The protocol for accessing the one-wire A-to-D converter via theone-wire port is as follows: (1) Initialization, (2) ROM FunctionCommand, (3) Memory/Convert Function Command, and (4) Transaction/Data.

[0063] All transactions on the one-wire bus 16 begin with aninitialization sequence. The initialization sequence consists of a resetpulse transmitted by the bus master 40 followed by presence pulse(s)transmitted by the slave(s).

[0064] The presence pulse lets the bus master 40 know that the one-wireA-to-D converter 10 is on the bus 16 and is ready to operate. Once thebus master 40 has detected a presence, it can issue one of the seven ROMfunction commands. All ROM function commands are eight bits long.

[0065] READ ROM:

[0066] This command allows the bus master 40 to read the one-wire A-to-Dconverter's 8-bit family code, unique 48-bit serial number, and 8-bitCRC. This command can only be used if there is a single one-wire A-to-Dconverter 10 on the bus. If more than one slave is present on the bus, adata collision will occur when all slaves try to transmit at the sametime (open drain will produce a wired-AND result). The resultant familycode and 48-bit serial number will result in a mismatch of the CRC.

[0067] MATCH ROM:

[0068] The match ROM command, followed by a 64-bit ROM sequence, allowsthe bus master 40 to address a specific one-wire A-to-D converter 10 ona multidrop bus. Only the one-wire A-to-D converter that exactly matchesthe 64-bit ROM sequence will respond to the following memory/convertfunction command. All slaves that do not match the 64-bit ROM sequencewill wait for a reset pulse. This command can be used with a single ormultiple devices on the bus.

[0069] SKIP ROM: This command can save time in a single drop bus systemby allowing the bus master 40 to access the memory/convert functionswithout providing the 64-bit ROM code. If more than one slave is presenton the bus and a read command is issued following the Skip ROM command,data collision will occur on the bus as multiple slaves transmitsimultaneously (open drain pull-downs will produce a wired-AND result).

[0070] SEARCH ROM:

[0071] When a system is initially brought up, the bus master might notknow the number of devices on the one-wire bus and their 64-bit ROMcodes. The search ROM command allows the bus master to use a process ofelimination to identify the 64-bit ROM codes of all slave devices on thebus. The search ROM process is the repetition of a simple 3-steproutine: read a bit, read the complement of the bit, then write thedesired value of that bit. The bus master performs this simple, 3-steproutine on each bit of the ROM. After one complete pass, the bus masterknows the contents of the ROM in one device. The remaining number ofdevices and their ROM codes may be identified by additional passes.

[0072] CONDITIONAL SEARCH: The Conditional Search ROM command operatessimilarly to the Search ROM command except that only devices fulfillingthe specified condition will participate in the search. The one-wireA-to-D converter device will respond to the Conditional Search commandif a channels alarm enable flags AEH and/or AEL are set and theconversion results in a value outside the range specified by thechannel's alarm threshold voltages. The Conditional Search ROM providesan efficient means for the bus master to determine devices on amultidrop system that have to signal an important event, such as avoltage leaving the tolerance band. After each pass of the ConditionalSearch that successfully determined the 64-bit ROM for a specific deviceon the multidrop bus, that particular device can be individuallyaccessed as if a Match ROM had been issued since all other devices willhave dropped out of the search process and are waiting for a resetpulse.

[0073] OVERDRIVE SKIP ROM:

[0074] On a single-drop bus this command can save time by allowing thebus master to access the memory/convert functions without providing the64-bit ROM code. Unlike the normal Skip ROM command the Overdrive SkipROM sets the one-wire A-to-D converter device in the Overdrive Mode(OD=1). All communication following this command has to occur atOverdrive Speed until a reset pulse of minimum 480 μs duration resetsall devices on the bus to regular speed (OD=0).

[0075] When issued on a multidrop bus this command will set allOverdrive-supporting devices into Overdrive mode. To subsequentlyaddress a specific Overdrive-supporting device, a reset pulse atOverdrive speed has to be issued followed by a Match ROM or Search ROMcommand sequence. This will speed up the time for the search process. Ifmore than one slave supporting Overdrive is present on the bus and theOverdrive Skip ROM command is followed by a read command, data collisionwill occur on the bus as multiple slaves transmit simultaneously (opendrain pull-downs will produce a wired-AND result).

[0076] OVERDRIVE MATCH ROM:

[0077] The Overdrive Match ROM command, followed by a 64-bit ROMsequence transmitted at Overdrive Speed, allows the bus master toaddress a specific one-wire A-to-D converter device that exactly matchesthe 64-bit ROM sequence will respond to the subsequent memory/convertfunction command. Slaves already in Overdrive mode from a previousOverdrive Skip or Match command will remain in Overdrive mode. All otherslaves that do not match the 64-bit ROM sequence or do not supportOverdrive will return to or remain at regular speed and wait for a resetpulse of minimum 480 μs duration. The Overdrive Match ROM command can beused with a single or multiple devices on the bus.

[0078] ONE-WIRE SIGNALING:

[0079] The one-wire A-to-D converter requires protocols to insure dataintegrity. The preferred protocol consists of four types of signaling onone line: reset sequence with reset pulse and presence pulse, Write 0,Write 1 and Read Data. All these signals except presence pulse areinitiated by the bus master. The one-wire A-to-D converter cancommunicate at two different speeds, regular speed and Overdrive Speed.If not explicitly set into the Overdrive mode, the one-wire A-to-Dconverter will communicate at regular speed.

[0080] As is clearly seen, the present invention is significant in theanalog-to-digital converter arena. The present invention is believed tobe especially effective when configured an employed as described herein,however, those skilled in the art will readily recognize that numerousvariations and substitutions may be made in the invention and its useand configuration to achieve substantially the same results as achievedby the embodiments and, in particular, the preferred embodimentdescribed herein. Each variation is intended to be included in thedescription herein and forms a part of the present invention. Theforegoing detailed description is, thus, to be clearly understood asbeing given by way of illustration and example only, the spirit andscope of the present invention being limited solely by the appendedclaims.

What is claimed is:
 1. An integrated circuit for converting an analogsignal to a digital signal and providing said digital signal to a hostdevice via a single wire data bus, said integrated circuit comprising:input/output circuitry for connecting to said single wire data bus;analog to digital conversion circuitry for providing a digital signal tosaid input/output circuitry; an analog input for connecting an analogsignal source and for providing an analog signal to said analog todigital conversion circuitry; and an EPROM memory for storing trim codesfor calibrating said analog to digital conversion circuitry.
 2. Theintegrated circuit of claim 1 , wherein said analog input comprises fouranalog input connections connected to a four to one multiplexer, saidmultiplexer providing one of said four analog input connections to saidanalog to digital conversion circuitry.
 3. The integrated circuit ofclaim 1 , wherein said integrated circuit operates parasitically fromsaid single wire data bus.
 4. The integrated circuit of claim 1 ,wherein said analog to digital conversion circuitry is configurable toprovide a plurality of conversion resolutions.
 5. The integrated circuitof claim if wherein said integrated circuit uses less than 5 miliwattsof power while active.
 6. The integrated circuit of claim 1 , whereinsaid single wire data bus utilizes a One-Wire data protocol.
 7. Ananalog to digital converter comprising: at least one analog input forreceiving an analog signal from an external analog signal producingdevice; an analog to digital conversion circuit; means for connectingsaid at least one analog input to said digital conversion circuit; aplurality of registers for storing an output of said analog to digitalconversion circuit; and input/output circuitry for retrieving saidoutput of said analog to digital conversion circuit and providing saidoutput to a single wire bus.
 8. The analog to digital converter of claim7 , wherein said means connecting said at least one analog input to saiddigital conversion circuit comprises a MUX circuit with an input fromthe at least one analog input and an output to said analog to digitalconversion circuit.
 9. The analog to digital converter of claim 7 ,wherein said analog to digital converter is powered parasitically fromsaid single wire bus.
 10. The analog to digital converter of claim 7 ,further comprising EPROM circuitry for storing trim code information,said trim code information comprising information for calibrating saidanalog to digital conversion circuitry.
 11. The analog to digitalconverter of claim 7 , wherein said analog to digital converter can beprogrammed to convert each one of said at least one analog inputs to adigital signal with a different resolution.
 12. The analog to digitalconverter of claim 7 , wherein said plurality of registers can alsostore alarm conditions indicating that said analog input is above orbelow a predetermined voltage.